The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a functional block diagram of a hard disk drive (HDD) 100 is depicted. The HDD 100 includes a hard disk assembly (HDA) 101 and a HDD printed circuit board (PCB) 102. The HDA 101 may include a magnetic medium 103, such as one or more platters that store data, and a read/write device 104. The read/write device 104 may be arranged on an actuator arm 105 and may read and write data on the magnetic medium 103.
Additionally, the HDA 101 includes a spindle motor 106 that rotates the magnetic medium 103 and a voice-coil motor (VCM) 107 that actuates the actuator arm 105. A preamplifier device 108 amplifies signals generated by the read/write device 104 during read operations and provides signals to the read/write device 104 during write operations.
The HDD PCB 102 includes a read/write channel module (hereinafter, “read channel”) 109, a hard disk controller (HDC) module 110, volatile memory 111, nonvolatile memory 112, a processor 113, and a spindle/VCM driver module 114. The read channel 109 processes data received from and transmitted to the preamplifier device 108.
The HDC module 110 controls components of the HDA 101 and communicates with a host device (not shown) via an I/O interface 115. The host device may include a computer, a multimedia device, a mobile computing device, etc. The I/O interface 115 may include wireline and/or wireless communication links.
The HDC module 110 may receive data from the HDA 101, the read channel 109, volatile memory 111, nonvolatile memory 112, the processor 113, the spindle/VCM driver module 114, and/or the I/O interface 115. The processor 113 may process the data, including encoding, decoding, filtering, and/or formatting.
The processed data may be output to the HDA 101, the read channel 109, volatile memory 111, nonvolatile memory 112, the processor 113, the spindle/VCM driver module 114, and/or the I/O interface 115. The spindle/VCM driver module 114 controls the spindle motor 106 and the VCM 107. The HDD PCB 102 includes a power supply 116 that provides power to the components of the HDD 100. The HDC module 110 may use volatile memory 111 and/or nonvolatile memory 112 to store data related to the control and operation of the HDD 100.
Volatile memory 111 may include dynamic random access memory (DRAM), synchronous DRAM, Rambus DRAM, etc. Nonvolatile memory 112 may include flash memory (including NAND and NOR flash memory), static RAM, magnetic RAM, phase change memory, and multi-state memory, in which each memory cell has more than two states.
Referring now to FIG. 2, a functional block diagram of a hybrid HDD 150 is depicted. An HDD PCB 152 of the hybrid HDD 150 includes nonvolatile cache 154, which communicates with the HDC module 110. The nonvolatile cache 154 may include any suitable type of nonvolatile memory, such as flash memory. The nonvolatile cache 154 may store data waiting to be written to the HDA 101, data waiting to be read by the I/O interface 115, and/or temporary values.
The HDA 101 can be powered down, and data waiting to be written to the HDA 101 can be cached in the nonvolatile cache 154. Once the nonvolatile cache 154 fills with data waiting to be written, and/or upon the occurrence of other conditions, the HDA 101 is powered up and the cached data is written to the HDA 101.
Powering down the HDA 101 saves power and makes the hybrid HDD 150 less prone to failure as a result of impact and vibration. The nonvolatile cache 154 can also cache frequently accessed data. When this data is requested by the I/O interface 115, the data can be provided quickly from the nonvolatile cache 154 without delays due to seeking and rotational latencies of the HDA 101.
The nonvolatile cache 154 can also store data that allows the host device associated with the hybrid HDD 150 to quickly resume from a powered down state. When the host device is powered down or placed in hibernate mode, resume data required to quickly power up the host device can be stored in the nonvolatile cache 154. The resume data may include certain data stored in the HDA 101, the addresses of which are referred to as a pinned set. When hibernating, the resume data may include some or all of the contents of volatile memory of the host device.
In order to support these features, the nonvolatile cache 154 typically contains a large amount of nonvolatile semiconductor storage. For example only, the nonvolatile cache 154 may include 256 megabytes or 512 megabytes of storage. Nonvolatile semiconductor storage is typically expensive and typically also has a finite lifetime.